This is going to be wild!
Question 1:
Part A:
Design a combinational circuit that counts the Numbers of 1’s in 7-bit ( , … .) input and has 3-bit output. (, , ). And write the input equations.
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Execuse the messy wiring!

left as an exercise to the reader left as an exercise to the reader
Part B:
Design a 5-bit comparator that takes 2’s compelemnt. you can use comparators, adders, decoders, etc.
Question 2:
Part A:
What is the function of this circuit?
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Toggles every negative edge as long as X
is 1
Part B:
Reduce the state table (from the book)
Part C:
Draw the reduced state diagram of the table
Part D:
Implement it using T-Flip Flops
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This is left as an exercise to the reader.
Question 3:
(Left is A, Middle is B, Right is C)Part A:
Given the current state is ABC = 100
. What is the state for the next 7 cycles?
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Part B:
Convert the following D
-FF serial adder to a T
-FF:
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Easy Solution: Convert the T-FlipFlop back to a D-FlipFlop! (i.e,
implement a D-FlipFlop with a T-Flipflop)
Standard Solution: do the truth table, K-maps, equations, etc.
This is left as an exercise to the reader.
Part C:
Given that all the registers are set to 1011
, what is the value of
register A
after: 4
, 8
, 12
and 16
cycles. Initially, the Flip was
set to 0, (or Reset).
Also, Register B is always filled with 1011
every 4
cycles! I am just too lazy to
draw that :)
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We can see that after 4
cycles,
We can also see the carry of A’s sum
Initially
After 4 cycles:
After 8 cycles:
After 12 cycles:
After 16 cycles:
Part D:
Given the following truth table,
x | y | z | A | B | C | D |
---|---|---|---|---|---|---|
0 | 0 | 0 | 1 | 1 | 0 | 0 |
0 | 0 | 1 | 0 | 0 | 1 | 1 |
0 | 1 | 0 | 1 | 0 | 0 | 1 |
0 | 1 | 1 | 1 | 1 | 1 | 1 |
1 | 0 | 0 | 1 | 0 | 1 | 1 |
1 | 0 | 1 | 1 | 1 | 0 | 1 |
1 | 1 | 0 | 1 | 1 | 1 | 0 |
1 | 1 | 1 | 0 | 0 | 0 | 1 |
implement it using the following PAL
after filling the table.
Show Equations
Do the K-maps, then you get:
Show Simplified Equations
can be simplifed as Which can be furthur simplified as
Also if you are wondering how tf and are implemented using AND and OR gates, refer to the book.
Show Table
This is left as exercise to the reader.