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Final Exam: Digital Logic Design - EE232

Stay strong fren, you are almost done!

This is going to be wild!

Question 1:

Part A:

Design a combinational circuit that counts the Numbers of 1’s in 7-bit (I0I_0 I1I_1, … I6I_6.) input and has 3-bit output. (O0O_0, O1O_1, O3O_3). And write the input equations.

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Execuse the messy wiring!

7bit Adder
7bit Adder

O0=I0I1I2I7O_0 = I_0 \oplus I_1 \oplus I_2 … \oplus I_7 O1=O_1 = left as an exercise to the reader O3=O_3 = left as an exercise to the reader

Part B:

Design a 5-bit comparator that takes 2’s compelemnt. you can use comparators, adders, decoders, etc.

Question 2:

Part A:

What is the function of this circuit?

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Toggles every negative edge as long as X is 1

Part B:

Reduce the state table (from the book)

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State Table
State Table

Part C:

Draw the reduced state diagram of the table

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State Table
State Table

Part D:

Implement it using T-Flip Flops

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This is left as an exercise to the reader.

Question 3:

(Left is A, Middle is B, Right is C)

Part A:

Given the current state is ABC = 100. What is the state for the next 7 cycles?

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A(t+1)=BC A(t+1) = B \oplus C B(t+1)=A B(t+1) = A C(t+1)=C C(t+1) = C ABC(0)=100 ABC(0) = 100 ABC(1)=010 ABC(1) = 010 ABC(2)=101 ABC(2) = 101 ABC(3)=110 ABC(3) = 110 ABC(4)=111 ABC(4) = 111 ABC(5)=011 ABC(5) = 011 ABC(6)=001 ABC(6) = 001 ABC(7)=100 ABC(7) = 100

Part B:

Convert the following D-FF serial adder to a T-FF:

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Easy Solution: Convert the T-FlipFlop back to a D-FlipFlop! (i.e, implement a D-FlipFlop with a T-Flipflop)
Standard Solution: do the truth table, K-maps, equations, etc.
This is left as an exercise to the reader.

Part C:

Given that all the registers are set to 1011, what is the value of register A after: 4, 8, 12 and 16 cycles. Initially, the Flip was set to 0, (or Reset).

Also, Register B is always filled with 1011 every 4 cycles! I am just too lazy to draw that :)

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We can see that after 4 cycles, A(t+4)=A+B+CA(t+4)=A + B + C
We can also see the C=C= carry of A’s sum
Initially A(0)=0 A (0) = 0 C(0)=0 C (0) = 0 After 4 cycles: A(4)=1011+1011+0=0110 A (4) = 1011 + 1011 + 0 = 0110 C(4)=1 C (4) = 1

After 8 cycles: A(8)=0110+1011+1=0010 A (8) = 0110 + 1011 + 1 = 0010 C(8)=1 C (8) = 1

After 12 cycles: A(12)=0010+1011+1=0010 A (12) = 0010 + 1011 + 1 = 0010 C(12)=1 C (12) = 1

After 16 cycles: A(16)=0110+1011+1=1110 A (16) = 0110 + 1011 + 1 = 1110 C(16)=0 C (16) = 0

Part D:

Given the following truth table,

xyzABCD
0001100
0010011
0101001
0111111
1001011
1011101
1101110
1110001

implement it using the following PAL after filling the table.

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Do the K-maps, then you get:
A=zˉ+xy A = \bar{z} + x \oplus y B=xyz B = \overline{x \oplus y \oplus z} C=xz C = x \oplus z D=z+xy D = z + x \oplus y

Show Simplified Equations

BB can be simplifed as B=yC B = \overline{y \oplus C } Which can be furthur simplified as B=yˉC B = \bar{y} \oplus C

Also if you are wondering how tf \oplus and ˉ\bar{\oplus} are implemented using AND and OR gates, refer to the book.

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This is left as exercise to the reader.

Show Connections

PAL
PAL

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